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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-22 12:28:07 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-27 22:48:06 +0100 |
| commit | f1e3c763b3eef15dbfae73f485408a0dec230d00 (patch) | |
| tree | 28682b0d4ad36063b3612c8a774af868a3e55878 /src/cpu/intel | |
| parent | 91fac61240612291f7be3362f7acad31803e8b03 (diff) | |
CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.
TODO: Check TSEG alignment, it used for MTRR programming.
Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index bd2513f5e2..1af5259715 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -133,7 +133,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; - top_of_ram = get_top_of_ram(); + top_of_ram = (uint32_t)cbmem_top(); /* Cache 8MiB below the top of ram. On haswell systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later @@ -318,7 +318,7 @@ struct ramstage_cache *ramstage_cache_location(long *size) /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of ram is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET); + return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } void ramstage_cache_invalid(struct ramstage_cache *cache) |