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| author | Vaibhav Shankar <vaibhav.shankar@intel.com> | 2016-08-23 17:56:17 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-09-14 22:17:47 +0200 |
| commit | ef8deaffcbfb68c5b15cdc9c91607fce5734ec8b (patch) | |
| tree | f595da26856df4dc4214837f339dae53ec481d20 /src/cpu/intel | |
| parent | 9e81540b85c6d06c7c3c63447b92f09590f032d1 (diff) | |
soc/intel/apollolake: Add PM methods to power gate PCIe
This implements GNVS variable to store the address of PERST_0,
_ON/_OFF methods to power gate PCIe during S0ix entry, and
PERST_0 assertion/de-assertion methods.
BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.
Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/intel')
0 files changed, 0 insertions, 0 deletions