diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 22:48:35 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-18 21:00:30 +0100 |
| commit | bfca67078cfddc18994fa6bbe9094a2ecca275a3 (patch) | |
| tree | d251389ecf692dab90b16af9dfe643fd1b71386e /src/cpu/intel | |
| parent | de01136484c58d13457ccf1e42fdb2310f3cbe65 (diff) | |
intel/sandybridge post-car: Redo MTRR settings and stack selection
Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Also fixes regression of slower S3 resume path after commit
9b99152 intel/sandybridge: Use common ACPI S3 recovery
Skipping low memory backup and using stage cache for ramstage decreases
time spent on S3 resume path by 50 ms on samsung/lumpy.
Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15790
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 56 |
1 files changed, 23 insertions, 33 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index d51fd01c05..f0d49390ba 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -174,10 +174,9 @@ before_romstage: post_code(0x29) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. - */ + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ movl %eax, %esp post_code(0x30) @@ -210,14 +209,6 @@ before_romstage: andl $~1, %eax wrmsr - /* Clear MTRR that was used to cache MRC */ - xorl %eax, %eax - xorl %edx, %edx - movl $MTRR_PHYS_BASE(2), %ecx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - wrmsr - post_code(0x33) /* Enable cache. */ @@ -234,32 +225,31 @@ before_romstage: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first MB - * and ramstage. - */ + /* Get number of MTRRs. */ + popl %ebx movl $MTRR_PHYS_BASE(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(0), %ecx - movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx // 36bit address space +1: + testl %ebx, %ebx + jz 1f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ wrmsr - -#if CACHE_ROM_SIZE - /* Enable Caching and speculative Reads for the - * complete ROM now that we actually have RAM. - */ - movl $MTRR_PHYS_BASE(1), %ecx - movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ wrmsr -#endif + inc %ecx + dec %ebx + jmp 1b +1: post_code(0x39) /* And enable cache again after setting MTRRs. */ |