diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-03 10:29:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-04 11:38:38 +0000 |
| commit | bc78e014c548ae6e6689050735875120036d0da8 (patch) | |
| tree | fc6a6d591972a10f88148e37cdd0e91235fdc6ed /src/cpu/intel | |
| parent | a751eec799d00058fe0f40653ab831f0a4b8aeab (diff) | |
cpu/intel/car/p4-netburst: Remove delay loops
While commented as 10 ms + 250 us, those delay loops actually
accounted for a total of 840 ms. And they seem unnecessary
as followup code has potentially infinite retries when
polling for status changes.
Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x.
Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 2cd0c5e922..58e411dcc3 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -177,12 +177,6 @@ cores_counted: hyper_threading_cpu: - /* delay 10 ms */ - movl $10000, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x25) /* Send Start IPI to all excluding ourself. */ @@ -198,12 +192,6 @@ hyper_threading_cpu: andl $LAPIC_ICR_BUSY, %ecx jnz 1b - /* delay 250 us */ - movl $250, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x26) /* Wait for sibling CPU to start. */ |