diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-01-13 09:33:03 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-05 12:50:43 +0000 |
| commit | a5b06b9b578f48b30502bba04841f06cf9ce9e4a (patch) | |
| tree | 1faeb24e3bfa252e5a1098d34f3547c5ee8251f4 /src/cpu/intel | |
| parent | f151cd2859b70722de3b17ee56929fc896cd22a1 (diff) | |
cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB
This fixes building lenovo/x200 with VBOOT.
All supported CPUs have enough L2 cache to support this.
Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/socket_BGA956/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index b56fb88677..7c42722e82 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -10,7 +10,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex - default 0x8000 + default 0x10000 config DCACHE_BSP_STACK_SIZE hex |