summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorElyes Haouas <ehaouas@noos.fr>2022-11-12 08:09:16 +0100
committerMartin L Roth <gaumless@gmail.com>2022-11-21 18:42:17 +0000
commit9aea4ec9a5d8c332d6682d05c78f010bba193e6f (patch)
tree984b714201e12b889993bb777880234f1ac12060 /src/cpu/intel
parentb04eda2ca1f5a40edcabd4933c9d0e6e120f6db0 (diff)
cpu/intel/socket_*: Clean up Kconfig files
Remove SSE when SSE is already selected by supported CPUs. Add "config SOCKET_SPECIFIC_OPTIONS" section to socket_p/Kconfig. Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/socket_441/Kconfig1
-rw-r--r--src/cpu/intel/socket_BGA956/Kconfig8
-rw-r--r--src/cpu/intel/socket_p/Kconfig7
3 files changed, 10 insertions, 6 deletions
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index 5b6ae7f61d..2ff419b2a0 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -7,7 +7,6 @@ config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_106CX
select MMX
- select SSE
select SETUP_XIP_CACHE
config DCACHE_RAM_BASE
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 638653c162..464a9b4679 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -1,11 +1,13 @@
config CPU_INTEL_SOCKET_BGA956
bool
- select CPU_INTEL_MODEL_1067X
- select MMX
- select SSE
if CPU_INTEL_SOCKET_BGA956
+config SOCKET_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_INTEL_MODEL_1067X
+ select MMX
+
config DCACHE_RAM_BASE
hex
default 0xfefc0000
diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig
index 552ed7088c..e90b42a7f7 100644
--- a/src/cpu/intel/socket_p/Kconfig
+++ b/src/cpu/intel/socket_p/Kconfig
@@ -1,11 +1,14 @@
config CPU_INTEL_SOCKET_P
bool
+
+if CPU_INTEL_SOCKET_P
+
+config SOCKET_SPECIFIC_OPTIONS
+ def_bool y
select CPU_INTEL_MODEL_1067X
select CPU_INTEL_MODEL_6FX
select MMX
-if CPU_INTEL_SOCKET_P
-
config DCACHE_RAM_BASE
hex
default 0xfefc0000