diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-23 19:54:12 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-24 16:12:44 +0000 |
| commit | 9796f60c62f57ac512f225809c10b5b09ef80f5a (patch) | |
| tree | 5d6c3e1d933782bbb03af4ac7a21579f722b5327 /src/cpu/intel | |
| parent | a40032780fe4da7d95b203fb3d05a25183590952 (diff) | |
coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 6adb8be9ce..9c238ca578 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -274,7 +274,6 @@ void romstage_common(const struct romstage_params *params) if (CONFIG_LPC_TPM) { init_tpm(wake_from_s3); } - timestamp_add_now(TS_END_ROMSTAGE); } static inline void prepare_for_resume(struct romstage_handoff *handoff) |