cpu: Get rid of unnecessary blank line {before,after} barce

Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>

7 files changed, 0 insertions, 10 deletions

diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index f20d446b5c..5e5fa813c6 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -313,7 +313,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * CPU_BCLK;
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 829d3b0b00..bb2edfa07d 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -217,7 +217,6 @@ static const void *find_cbfs_microcode(void)
 			struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
 
 			for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) {
-
 				if ((sig == entry->sig) && (pf & entry->pf)) {
 					return ucode_updates;
 				}
diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c
index 11899c615d..9d11ef053d 100644
--- a/src/cpu/intel/model_2065x/acpi.c
+++ b/src/cpu/intel/model_2065x/acpi.c
@@ -185,7 +185,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * IRONLAKE_BCLK + ratio / 3;
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
index f1d03c8961..08548c5f45 100644
--- a/src/cpu/intel/model_206ax/acpi.c
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -286,7 +286,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * SANDYBRIDGE_BCLK;
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 6c44778cba..8bb1091687 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -324,7 +324,6 @@ static void model_206ax_report(void)
 
 static void model_206ax_init(struct device *cpu)
 {
-
 	/* Clear out pending MCEs */
 	/* This should only be done on a cold boot */
 	mca_clear_status();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index a481a674f6..ff64ab18e4 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -89,7 +89,6 @@ static void configure_misc(void)
 	msr = rdmsr(IA32_PECI_CTL);
 	msr.lo |= 1;
 	wrmsr(IA32_PECI_CTL, msr);
-
 }
 
 #define PIC_SENS_CFG	0x1aa
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
index 2a273168f3..fa433660b6 100644
--- a/src/cpu/intel/slot_1/l2_cache.c
+++ b/src/cpu/intel/slot_1/l2_cache.c
@@ -244,7 +244,6 @@ int read_l2(u32 address)
 	/* If OK then get the result from BBL_CR_ADDR */
 	msr = rdmsr(BBL_CR_ADDR);
 	return (msr.lo >> 0x15);
-
 }
 
 /* Write data into the L2 controller register at address */
@@ -270,7 +269,6 @@ int write_l2(u32 address, u32 data)
 	 */
 
 	for (i = 0; i < v2; i++) {
-
 		u32 data1, data2;
 		// Bits legend
 		// data1   = ffffffff
@@ -352,7 +350,6 @@ int calculate_l2_cache_size(void)
 		 */
 		for (cache_setting = BBLCR3_L2_SIZE_256K;
 		     cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) {
-
 			eax = bblcr3 | cache_setting;
 			msr.lo = eax;
 			wrmsr(BBL_CR_CTL3, msr);
@@ -726,7 +723,6 @@ int p6_configure_l2_cache(void)
 	/* Write to all cache lines to initialize */
 
 	while (cache_size > 0) {
-
 		/* Each cache line is 32 bytes. */
 		cache_size -= 32;