diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-07-05 21:18:50 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-08 13:11:59 +0000 |
| commit | 3edf840ad15154d38769c0115811906284762b11 (patch) | |
| tree | 02b55264c698b3c0fb1422f41ceecf6424a0ae20 /src/cpu/intel | |
| parent | cdea508a024376c79c8cf29648ba174867eb2750 (diff) | |
cpu/x86/64bit: Turn jumping to long mode into a macro
This makes it easier to reuse, e.g. if you want to do it twice in one
assembly file.
Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/core2/cache_as_ram.S | 4 | ||||
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 4 | ||||
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 3 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index e134717b40..2e4d9c8074 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/64bit/entry64.inc> .section .init .global bootblock_pre_c_entry @@ -162,8 +163,7 @@ addrsize_set_high: subl $4, %esp #if ENV_X86_64 - - #include <cpu/x86/64bit/entry64.inc> + setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 76986ff68e..578bf03afd 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/64bit/entry64.inc> #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e @@ -213,8 +214,7 @@ end_microcode_update: andl $0xfffffff0, %esp #if ENV_X86_64 - - #include <cpu/x86/64bit/entry64.inc> + setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index f7c023b402..32fddd6810 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -13,6 +13,7 @@ .global bootblock_pre_c_entry #include <cpu/intel/car/cache_as_ram_symbols.inc> +#include <cpu/x86/64bit/entry64.inc> .code32 _cache_as_ram_setup: @@ -362,7 +363,7 @@ fill_cache: subl $4, %esp #if ENV_X86_64 - #include <cpu/x86/64bit/entry64.inc> + setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) movd %mm2, %rdi shlq $32, %rdi /* BIST */ |