diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-01-27 01:11:20 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-01-27 01:11:20 +0000 |
| commit | ce952652a1099b71fcd6e7ad24bb6edad50ba6d1 (patch) | |
| tree | 21c8c9e36b82b5c92cc04bd94200869f8bc9ac5f /src/cpu/intel | |
| parent | 33ee3ee6b4b0432bb9958b9d959f4783856b37ff (diff) | |
oops. this is weird. CAR addresses should be specified in the socket and not in
the board. I thought we did this ages ago.
Also push CAR BASE further down so it won't conflict with a 32mbit flash part.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/socket_441/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/intel/socket_mFCPGA478/Kconfig | 19 |
2 files changed, 20 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 1306656fb3..f73c8a9e70 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy config DCACHE_RAM_BASE hex - default 0xffdf8000 + default 0xffaf8000 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index b8a3508dd2..3f39303065 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -1,3 +1,22 @@ config CPU_INTEL_SOCKET_MFCPGA478 bool + +if CPU_INTEL_SOCKET_MFCPGA478 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_INTEL_CORE + select CPU_INTEL_CORE2 + select MMX + select SSE select CACHE_AS_RAM + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif |