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| author | Zheng Bao <fishbaozi@gmail.com> | 2020-12-21 13:56:22 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-26 15:51:36 +0000 |
| commit | 64d0ad347b5c9c698547f0ff15779e88a10014f4 (patch) | |
| tree | 856520b4def372b359d5441ae92f30eae9e9cdeb /src/cpu/intel | |
| parent | 56868b8045aed351a2bb0fe74cd43cf78966c3ce (diff) | |
soc/amd: Add an option to select if SOC supports ESPI sub decode
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.
Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/cpu/intel')
0 files changed, 0 insertions, 0 deletions