diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-08-07 14:44:51 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-08-09 00:38:39 +0200 |
| commit | 0db6820b10c3452764ab62173c3b75cefbf6c215 (patch) | |
| tree | 95abc6378ed60c37e14de842a7baf014dc60111b /src/cpu/intel | |
| parent | 4c29d7f27d315ab93c811fb86ba246151dc84da3 (diff) | |
Synchronize rdtsc instructions
The CPU can arbitrarily reorder calls to rdtsc, significantly
reducing the precision of timing using the CPUs time stamp counter.
Unfortunately the method of synchronizing rdtsc is different
on AMD and Intel CPUs. There is a generic method, using the cpuid
instruction, but that uses up a lot of registers, and is very slow.
Hence, use the correct lfence/mfence instructions (for CPUs that
we know support it)
Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1422
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/model_1067x/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/Kconfig | 1 |
5 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index b079922275..852c9cdf0c 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_1067X bool select SMP select SSE2 + select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 103ed50d3e..7a75ec1ba3 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -4,9 +4,9 @@ config CPU_INTEL_MODEL_106CX select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE config CPU_ADDR_BITS int default 32 - diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 9cc6edd94e..6635868453 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select MICROCODE_IN_CBFS #select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 31d24bd68f..e2b1986132 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6EX select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 851685cb06..4517f17fa6 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6FX select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE |