diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-01-28 12:20:42 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-28 12:34:52 +0000 |
| commit | 93cb1809a2034aa398ad0cb5faf7d5e8e48bfe44 (patch) | |
| tree | 036465f6867dda03a8a164d802beda00f0d95ee0 /src/cpu/intel | |
| parent | dd5fe14759635b1bb4cacde77df79233d65dbadc (diff) | |
cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE
This fixes a regression introduced by
Commit 985821c (cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE)
where the CAR base is not aligned to its size.
Change-Id: If54cb178e86426e1491dda4047302632d876a8f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50029
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/socket_LGA775/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 537a0d1c5f..3ce106a394 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -25,6 +25,6 @@ config DCACHE_BSP_STACK_SIZE config DCACHE_RAM_BASE hex - default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE + default 0xfeff8000 # 4GB - 16MB - DCACHE_RAM_SIZE endif # CPU_INTEL_SOCKET_LGA775 |