diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-01-17 11:13:46 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-19 05:26:12 +0100 |
| commit | 8c20399a42a6bb76f537042b4d7ba725ac78f10c (patch) | |
| tree | 41a30750383c865dce1b9fde8265110f57f0a5fc /src/cpu/intel | |
| parent | 305b1f0d30b68c310d4dfa7e1a5f432769a65b31 (diff) | |
haswell: wait 10ms after INIT IPI
There should be a fixed 10ms wait after sending an INIT IPI. The
previous implementation was just waiting up to 10ms for the IPI to
complete the send. That is not correct. The 10ms is unconditional
according to the documentation. No ill effects were observed with the
previous behavior, but it's important to follow the documentation.
Change-Id: Ib31d49ac74808f6eb512310e9f54a8f4abc3bfd7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2780
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/mp_init.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index b1567ba3e4..3076d070ec 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -458,15 +458,8 @@ int start_aps(struct bus *cpu_bus, int ap_count) lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT); - printk(BIOS_DEBUG, "Waiting for INIT to complete..."); - - /* Wait for 10 ms to complete. */ - if (apic_wait_timeout(10000 /* 10 ms */, 100 /* us */)) { - printk(BIOS_DEBUG, "timed out. Bailing. \n"); - return -1; - } else { - printk(BIOS_DEBUG, "done.\n"); - } + printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); + mdelay(10); /* Send 1st SIPI */ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { |