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authorDuncan Laurie <dlaurie@chromium.org>2013-03-07 14:08:04 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-21 23:06:56 +0100
commit1ad5564dd675a246f5b0a05d03482836d49d44a9 (patch)
tree8a014191ef33991fb0417ba58093f8d5702d243d /src/cpu/intel
parent5cc51c08cd44e2749f4a27775cefffd4b91e0a50 (diff)
lynxpoint: Add helper functions for reading PM and GPIO base
These base addresses are used in several places and it is helpful to have one location that is reading it. Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2812 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/acpi.c4
-rw-r--r--src/cpu/intel/haswell/haswell_init.c2
2 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index c0df9f6f37..a4d9cd9292 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -33,6 +33,8 @@
#include "haswell.h"
#include "chip.h"
+#include <southbridge/intel/lynxpoint/pch.h>
+
static int get_cores_per_package(void)
{
struct cpuinfo_x86 c;
@@ -322,7 +324,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
void generate_cpu_entries(void)
{
int len_pr;
- int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+ int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
int numcpus = totalcores/cores_per_package;
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index c7f89ee646..0bb11a8ed0 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -267,7 +267,7 @@ static void configure_c_states(void)
msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
msr.lo &= ~0x7ffff;
- msr.lo |= (PMB0_BASE + 4); // LVL_2 base address
+ msr.lo |= (get_pmbase() + 4); // LVL_2 base address
msr.lo |= (2 << 16); // CST Range: C7 is max C-state
wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);