diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-29 00:18:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-21 11:27:07 +0000 |
| commit | 8e6f162cc0e8758d2d8853ece1b2d8a31e9bf313 (patch) | |
| tree | 3823f09e159456d53e7cfcd15539239c6835a786 /src/cpu/intel | |
| parent | e78e90918057a0d32a73b066c0eb2138229cc287 (diff) | |
cpu/intel/haswell: Add s0ix support
Backport Broadwell's s0ix support to Haswell in preparation to unify
both platforms' CPU code. Note that only ULT variants support s0ix.
This option is currently unused, but will be put to use in subsequent
commits, when switching Broadwell mainboards to use Haswell's CPU code.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46924
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/acpi.c | 25 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/chip.h | 3 |
2 files changed, 27 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 7c99df36c0..0f11e5f8d9 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,6 +14,12 @@ #include <southbridge/intel/lynxpoint/pch.h> +static int cstate_set_s0ix[3] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10, +}; + static int cstate_set_lp[3] = { C_STATE_C1E, C_STATE_C3, @@ -94,6 +100,21 @@ static void generate_T_state_entries(int core, int cores_per_package) ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } +static bool is_s0ix_enabled(void) +{ + if (!haswell_is_ult()) + return false; + + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (!lapic || !lapic->chip_info) + return false; + + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + return conf->s0ix_enable; +} + static void generate_C_state_entries(void) { acpi_cstate_t map[3]; @@ -111,7 +132,9 @@ static void generate_C_state_entries(void) if (!cpu || !cpu->cstates) return; - if (haswell_is_ult()) + if (is_s0ix_enabled()) + set = cstate_set_s0ix; + else if (haswell_is_ult()) set = cstate_set_lp; else set = cstate_set_trad; diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 16f1079c32..776e23903b 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -34,4 +34,7 @@ struct cpu_intel_haswell_config { int tcc_offset; /* TCC Activation Offset */ struct cpu_vr_config vr_config; + + /* Enable S0iX support */ + bool s0ix_enable; }; |