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| author | Sven Schnelle <svens@stackframe.org> | 2012-06-19 18:00:01 +0200 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2012-06-19 18:31:58 +0200 |
| commit | edac28ce65e48d6b2a0a2421d046a4fe4b2bf589 (patch) | |
| tree | 188779a36f71e55957f8186602e25588fc1ba96d /src/cpu/intel | |
| parent | 1a7a7e610e0fbc54fcc802bedbb31673dffff449 (diff) | |
Enable Intel PECI on Model 6fx CPUs
Those CPUs support the PECI (Platform Environment Control
Interface), so enable it. This interface is commonly used
for tasks like fan control.
Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1104
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 033dfe6639..106719ea7b 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -127,6 +127,8 @@ static void configure_c_states(void) } #define IA32_MISC_ENABLE 0x1a0 +#define IA32_PECI_CTL 0x5a0 + static void configure_misc(void) { msr_t msr; @@ -170,6 +172,12 @@ static void configure_misc(void) msr.lo |= vid_max; wrmsr(IA32_PERF_CTL, msr); + + /* Enable PECI */ + msr = rdmsr(IA32_PECI_CTL); + msr.lo |= 1; + wrmsr(IA32_PECI_CTL, msr); + } #define PIC_SENS_CFG 0x1aa |