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authorDavid Hendricks <dhendrix@chromium.org>2013-03-26 21:34:01 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-29 21:12:54 +0100
commite85f4eb1b0f63535ceb36315712a03d7d7f656ac (patch)
tree1d9b658ff09edb5ac35c63c24bb96c51e47c3ae6 /src/cpu/intel
parentdc82fc563486794005ada364f498167df9b686d6 (diff)
armv7: update sync barrier usage in dcache_op_set_way()
This moves the dsb() before the loop to sync any outstanding memory accesses, and adds an isb() after the loop to ensure all outstanding instructions are completed. Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2929 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
0 files changed, 0 insertions, 0 deletions