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authorArthur Heymans <arthur@aheymans.xyz>2021-05-29 07:30:33 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-06-07 12:54:39 +0000
commitbab9e2e6bdf3bbfa6047773a04632e0fbdf64afb (patch)
treeab42496f77d4bf76f3f9f79eea16ddc92d8a5cd6 /src/cpu/intel
parent11cac784ff788b4f0495758d7f5992e457ea552c (diff)
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that will be for a later commit. Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/car/romstage.c15
1 files changed, 3 insertions, 12 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index a307893c11..a2d1a89292 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -7,14 +7,14 @@
#include <arch/symbols.h>
#include <commonlib/helpers.h>
#include <program_loading.h>
-#include <timestamp.h>
+#include <romstage_common.h>
#include <security/vboot/vboot_common.h>
/* If we do not have a constrained _car_stack region size, use the
following as a guideline for acceptable stack usage. */
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
-static void romstage_main(void)
+void __noreturn romstage_main(void)
{
int i;
const int num_guards = 64;
@@ -54,14 +54,5 @@ static void romstage_main(void)
prepare_and_run_postcar();
/* We do not return here. */
-}
-
-asmlinkage void car_stage_entry(void)
-{
- timestamp_add_now(TS_ROMSTAGE_START);
-
- /* Assumes the hardware was set up during the bootblock */
- console_init();
-
- romstage_main();
+ die("failed to load postcar\n");
}