diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-02-06 17:01:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-08 15:11:13 +0000 |
| commit | a5aee116c3f51111b81fc6dd51cf286feffcbff8 (patch) | |
| tree | 6741a461cc51ae9e0f10784e3f9332308560e9d7 /src/cpu/intel | |
| parent | 5700149dbf3ddcb00500b9a8be8cb47e1527b6d9 (diff) | |
cpu/intel/model_206ax/model_206ax_init: use CPUID_ALL_STEPPINGS_MASK
Use CPUID_ALL_STEPPINGS_MASK to only need one CPU device ID table entry
per family & model combination and not one per stepping.
TEST=Thinkpad x230 with Ivy Bridge stepping 9 CPU still boots with this
patch applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46020d5b1b1fba8449c3823fac1369e5670d91c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72854
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index aecd61c86b..04a9d2dbf3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -427,16 +427,8 @@ static struct device_operations cpu_dev_ops = { }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x206a0, CPUID_EXACT_MATCH_MASK }, /* Intel Sandybridge */ - { X86_VENDOR_INTEL, 0x206a6, CPUID_EXACT_MATCH_MASK }, /* Intel Sandybridge D1 */ - { X86_VENDOR_INTEL, 0x206a7, CPUID_EXACT_MATCH_MASK }, /* Intel Sandybridge D2/J1 */ - { X86_VENDOR_INTEL, 0x306a0, CPUID_EXACT_MATCH_MASK }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a2, CPUID_EXACT_MATCH_MASK }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a4, CPUID_EXACT_MATCH_MASK }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a5, CPUID_EXACT_MATCH_MASK }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a6, CPUID_EXACT_MATCH_MASK }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a8, CPUID_EXACT_MATCH_MASK }, /* Intel IvyBridge */ - { X86_VENDOR_INTEL, 0x306a9, CPUID_EXACT_MATCH_MASK }, /* Intel IvyBridge */ + { X86_VENDOR_INTEL, 0x206a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel Sandybridge */ + { X86_VENDOR_INTEL, 0x306a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel IvyBridge */ { 0, 0, 0 }, }; |