cpu: Get rid of CPU_SPECIFIC_OPTIONS

Remove dummy CPU_SPECIFIC_OPTIONS.

Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76681
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 21 insertions, 54 deletions

diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 5b4f6fc752..5bcdd98ce9 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -1,11 +1,6 @@
 
 config CPU_INTEL_HASWELL
 	bool
-
-if CPU_INTEL_HASWELL
-
-config CPU_SPECIFIC_OPTIONS
-	def_bool y
 	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC
@@ -19,6 +14,8 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_ASAN_IN_ROMSTAGE
 	select CPU_INTEL_COMMON_VOLTAGE
 
+if CPU_INTEL_HASWELL
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index bced054de9..a8d445c5f1 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -1,10 +1,5 @@
 config CPU_INTEL_MODEL_2065X
 	bool
-
-if CPU_INTEL_MODEL_2065X
-
-config CPU_SPECIFIC_OPTIONS
-	def_bool y
 	select HAVE_EXP_X86_64_SUPPORT
 	select ARCH_X86
 	select SSE2
@@ -16,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 
+if CPU_INTEL_MODEL_2065X
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 479dbbb223..10c0ae3d3e 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -1,10 +1,5 @@
 config CPU_INTEL_MODEL_206AX
 	bool
-
-if CPU_INTEL_MODEL_206AX
-
-config CPU_SPECIFIC_OPTIONS
-	def_bool y
 	select ARCH_X86
 	select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT
 	select SSE2
@@ -16,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 
+if CPU_INTEL_MODEL_206AX
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index c30e066444..4ba8747012 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -2,11 +2,6 @@
 
 config CPU_INTEL_SLOT_1
 	bool
-
-if CPU_INTEL_SLOT_1
-
-config SLOT_SPECIFIC_OPTIONS
-	def_bool y
 	select CPU_INTEL_MODEL_65X
 	select CPU_INTEL_MODEL_67X
 	select CPU_INTEL_MODEL_68X
@@ -19,6 +14,8 @@ config SLOT_SPECIFIC_OPTIONS
 	select SETUP_XIP_CACHE
 	select RESERVE_MTRRS_FOR_OS
 
+if CPU_INTEL_SLOT_1
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index ca6990db23..1a549ac328 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -1,13 +1,10 @@
 config CPU_INTEL_SOCKET_441
 	bool
-
-if CPU_INTEL_SOCKET_441
-
-config SOCKET_SPECIFIC_OPTIONS
-	def_bool y
 	select CPU_INTEL_MODEL_106CX
 	select SETUP_XIP_CACHE
 
+if CPU_INTEL_SOCKET_441
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 84bb06dabc..b56fb88677 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -1,12 +1,9 @@
 config CPU_INTEL_SOCKET_BGA956
 	bool
+	select CPU_INTEL_MODEL_1067X
 
 if CPU_INTEL_SOCKET_BGA956
 
-config SOCKET_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_INTEL_MODEL_1067X
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index 9f1fbbbdfc..223f80d228 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -1,15 +1,12 @@
 config CPU_INTEL_SOCKET_FCBGA559
 	bool
+	select CPU_INTEL_MODEL_106CX
+	select CPU_HAS_L2_ENABLE_MSR
 	help
 	  Select this socket on Intel Pineview
 
 if CPU_INTEL_SOCKET_FCBGA559
 
-config SOCKET_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_INTEL_MODEL_106CX
-	select CPU_HAS_L2_ENABLE_MSR
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 897b0328fe..63d6250c62 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -1,16 +1,13 @@
 config CPU_INTEL_SOCKET_LGA775
 	bool
-
-if CPU_INTEL_SOCKET_LGA775
-
-config SOCKET_SPECIFIC_OPTIONS
-	def_bool y
 	select CPU_INTEL_MODEL_6FX
 	select CPU_INTEL_MODEL_F3X
 	select CPU_INTEL_MODEL_F4X
 	select CPU_INTEL_MODEL_1067X
 	select SIPI_VECTOR_IN_ROM
 
+if CPU_INTEL_SOCKET_LGA775
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x8000 # 32 kB
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig
index 6285e823a5..2e653e97c1 100644
--- a/src/cpu/intel/socket_m/Kconfig
+++ b/src/cpu/intel/socket_m/Kconfig
@@ -1,13 +1,10 @@
 config CPU_INTEL_SOCKET_M
 	bool
-
-if CPU_INTEL_SOCKET_M
-
-config SOCKET_SPECIFIC_OPTIONS
-	def_bool y
 	select CPU_INTEL_MODEL_6EX
 	select CPU_INTEL_MODEL_6FX
 
+if CPU_INTEL_SOCKET_M
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index dcf0e98957..8f28670a1d 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -1,10 +1,5 @@
 config CPU_INTEL_SOCKET_MPGA604
 	bool
-
-if CPU_INTEL_SOCKET_MPGA604
-
-config SOCKET_SPECIFIC_OPTIONS
-	def_bool y
 	select CPU_INTEL_MODEL_F2X
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
@@ -12,6 +7,8 @@ config SOCKET_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 
+if CPU_INTEL_SOCKET_MPGA604
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000
diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig
index 12e078c69b..90bfdc99da 100644
--- a/src/cpu/intel/socket_p/Kconfig
+++ b/src/cpu/intel/socket_p/Kconfig
@@ -1,13 +1,10 @@
 config CPU_INTEL_SOCKET_P
 	bool
-
-if CPU_INTEL_SOCKET_P
-
-config SOCKET_SPECIFIC_OPTIONS
-	def_bool y
 	select CPU_INTEL_MODEL_1067X
 	select CPU_INTEL_MODEL_6FX
 
+if CPU_INTEL_SOCKET_P
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000