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authorYinghai Lu <yinghailu@gmail.com>2005-07-08 02:49:49 +0000
committerYinghai Lu <yinghailu@gmail.com>2005-07-08 02:49:49 +0000
commit13f1c2af8be2cd7f7e99a678f5d428a65b771811 (patch)
tree27cad5581f1fa150f573149d48e82f70ba1b1d9f /src/cpu/intel
parent14cde9e96a777f9d75016a13b23fab0480515f58 (diff)
eric patch
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_f0x/model_f0x_init.c2
-rw-r--r--src/cpu/intel/model_f1x/model_f1x_init.c2
-rw-r--r--src/cpu/intel/model_f2x/model_f2x_init.c2
-rw-r--r--src/cpu/intel/model_f3x/model_f3x_init.c2
-rw-r--r--src/cpu/intel/model_f4x/Config.lb12
-rw-r--r--src/cpu/intel/model_f4x/microcode_MBDF410D.h1024
-rw-r--r--src/cpu/intel/model_f4x/model_f4x_init.c58
-rw-r--r--src/cpu/intel/socket_mPGA604_800Mhz/Config.lb1
8 files changed, 1099 insertions, 4 deletions
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 55504a1049..474d025799 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -30,7 +30,7 @@ static void model_f0x_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 53cee4fe68..42dff1e276 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -30,7 +30,7 @@ static void model_f1x_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 4f69d81d2a..f019ea4473 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -34,7 +34,7 @@ static void model_f2x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index a89e7d1782..20b8518c7c 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f4x/Config.lb b/src/cpu/intel/model_f4x/Config.lb
new file mode 100644
index 0000000000..66f6ceb00f
--- /dev/null
+++ b/src/cpu/intel/model_f4x/Config.lb
@@ -0,0 +1,12 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+driver model_f4x_init.o
diff --git a/src/cpu/intel/model_f4x/microcode_MBDF410D.h b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
new file mode 100644
index 0000000000..9266ce5c34
--- /dev/null
+++ b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
@@ -0,0 +1,1024 @@
+0x00000001, /* Header Version */
+0x0000000d, /* Patch ID */
+0x11032004, /* DATE */
+0x00000f41, /* CPUID */
+0xa3430d74, /* Checksum */
+0x00000001, /* Loader Version */
+0x000000bd, /* Platform ID */
+0x00000fd0, /* Data size */
+0x00001000, /* Total size */
+0x00000000, /* reserved */
+0x00000000, /* reserved */
+0x00000000, /* reserved */
+0x23869663,
+0x00e8d132,
+0xc1efa329,
+0x20662968,
+0xb833cad6,
+0x78012780,
+0x0971cf44,
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diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
new file mode 100644
index 0000000000..649638670d
--- /dev/null
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -0,0 +1,58 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static uint32_t microcode_updates[] = {
+ /* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+#include "microcode_MBDF410D.h"
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
+static void model_f4x_init(device_t cpu)
+{
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+ x86_setup_mtrrs(36);
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+ /* Start up my cpu siblings */
+ intel_sibling_init(cpu);
+};
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_f4x_init,
+};
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x0f41 }, /* Xeon */
+ { 0, 0 },
+};
+
+static struct cpu_driver model_f4x __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb b/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
index 0b794338a2..2637c86594 100644
--- a/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
+++ b/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
@@ -1,3 +1,4 @@
config chip.h
object socket_mPGA604_800Mhz.o
dir /cpu/intel/model_f3x
+dir /cpu/intel/model_f4x