diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-04-01 16:49:31 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-04-03 19:25:42 +0200 |
| commit | 13cc952a13ea29d9c5016a861d97da8326c87c4e (patch) | |
| tree | a73ff988c077afc851fc79c0e0f327fac46db1b5 /src/cpu/intel | |
| parent | 0f0fe100cb27770d615a70d5a78310ad47cb1abf (diff) | |
haswell: keep ROM cache enabled
The MP code on haswell was mirroring the BSPs MTRRs. In addition it
was cleaning up the ROM cache so that the MTRR register values were
the same once the OS was booted. Since the hyperthread sibling of
the BSP was going through this path the ROM cache was getting torn
down once the hyperthread was brought up.
That said, there was no differnce in observed boot time keeping the
ROM cache enabled.
Change-Id: I2a59988fcfeea9291202c961636ea761c2538837
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3008
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/mp_init.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index cc1389247e..ddcff6c834 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -181,8 +181,12 @@ ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* Cleanup ROM caching. */ - cleanup_rom_caching(); + /* The MTRR resources are core scoped. Therefore, there is no need + * to do the same work twice. Additionally, this check keeps the + * ROM cache enabled on the BSP since its hyperthread sibling won't + * call cleanup_rom_caching(). */ + if ((lapicid() & 1) == 0) + cleanup_rom_caching(); /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ |