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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 17:22:00 +0300
committerMartin Roth <martinroth@google.com>2016-06-21 00:39:47 +0200
commit07921540dda79d810d8bfc6be211513c238a0d63 (patch)
tree6395b9d31d8030480004a6af8f1afc12394f678f /src/cpu/intel
parent633c57d1d1ab3b2241fd259e12423054527ee000 (diff)
intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc10
-rw-r--r--src/cpu/intel/slot_1/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_FC_PGA370/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_PGA370/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_mFCBGA479/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_mPGA479M/Makefile.inc1
6 files changed, 13 insertions, 2 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index e28d033837..349ec05f03 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -318,7 +318,12 @@ lout:
/* We need to set EBP? No need. */
movl %esp, %ebp
pushl %eax /* BIST */
- call main
+ call romstage_main
+
+ /* Save return value from romstage_main. It contains the stack to use
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
+ movl %eax, %ebx
/* We don't need CAR from now on. */
@@ -356,7 +361,8 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl $CONFIG_RAMTOP, %esp
+ /* Setup stack as indicated by return value from romstage_main(). */
+ movl %ebx, %esp
movl %esp, %ebp
call copy_and_run
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index 992000bcfd..512571d318 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -29,3 +29,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
index fb9accc3fa..cc6e299551 100644
--- a/src/cpu/intel/socket_FC_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
@@ -23,3 +23,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc
index 2aed7de24c..d0f54051d6 100644
--- a/src/cpu/intel/socket_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_PGA370/Makefile.inc
@@ -23,3 +23,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
index e247c0966d..c84659807a 100644
--- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc
+++ b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
@@ -7,3 +7,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc
index abade4e87e..2a3187a8c0 100644
--- a/src/cpu/intel/socket_mPGA479M/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc
@@ -10,3 +10,4 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c