diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-05-31 21:34:53 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:52:00 +0000 |
| commit | 0310d34c2f682b00431a052e770ad44656d1d6f6 (patch) | |
| tree | 89c249ae013acb6a6de33ef1adf3c302e276b8fe /src/cpu/intel | |
| parent | bdea3524b0452de08e409d9097d60f67b5afb455 (diff) | |
cpu/intel/microcode: Have provision to re-load microcode patch
This patch provides an option to reload the microcode patch a.k.a
second microcode patch if SoC selects the required
RELOAD_MICROCODE_PATCH config.
There is a new feature requirement starting with ADL to re-load the
microcode patch as per new Mcheck initialization flow.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS. Able to re-load
microcode patch as below:
[INFO ] microcode: Re-load microcode patch
[INFO ] microcode: updated to revision 0x41b date=2022-03-08
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a3c29b3c25fccd31280a2a5a8d4fb22a6cf53bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64833
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/microcode/Kconfig | 10 | ||||
| -rw-r--r-- | src/cpu/intel/microcode/microcode.c | 9 |
2 files changed, 17 insertions, 2 deletions
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index c7bbecbace..6e8acdc01d 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -5,3 +5,13 @@ config MICROCODE_UPDATE_PRE_RAM help Select this option if you want to update the microcode during the cache as RAM setup. + +config RELOAD_MICROCODE_PATCH + bool + default n + help + Select this option if SoC recommends to re-load microcode + patch as part of CPU multiprocessor initialization process. + This feature is mostly required with Intel latest generation + processors starting with Alder Lake (with modified MCHECK init + flow). diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 469bd25496..beadb489de 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -79,10 +79,15 @@ void intel_microcode_load_unlocked(const void *microcode_patch) current_rev = read_microcode_rev(); - /* No use loading the same revision. */ - if (current_rev == m->rev) { + /* + * No use loading the same revision unless RELOAD_MICROCODE_PATCH + * config is selected. + */ + if (!CONFIG(RELOAD_MICROCODE_PATCH) && (current_rev == m->rev)) { printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n"); return; + } else { + printk(BIOS_INFO, "microcode: Re-load microcode patch\n"); } #if ENV_RAMSTAGE |