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| author | Ivy Jian <ivy_jian@compal.corp-partner.google.com> | 2018-09-28 10:23:41 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-04 09:37:48 +0000 |
| commit | 0562c1e75820b05c4a278538496e8a3ffc660866 (patch) | |
| tree | 468d73794f85fad9c51a2ff2743a3655a050704b /src/cpu/intel | |
| parent | 3f59f082e3c1a0ffe382580a31ebfa8b58fc2785 (diff) | |
mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Fleex
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT.
BUG=b:116721822
TEST=Verified it in Fleex EVT board which rework ram id.
Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel')
0 files changed, 0 insertions, 0 deletions