summaryrefslogtreecommitdiff
path: root/src/cpu/intel/turbo
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2023-11-06 19:23:40 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-11-07 19:20:18 +0000
commite91785dfd8fd29a2f39a1f0ceb143015536706fb (patch)
tree8325c0414e021603b4e9250269d59768b6a099b1 /src/cpu/intel/turbo
parenta49e7b974d8a10642bc820eefdaa26c5b5b898f5 (diff)
soc/amd/common,stoneyridge: drop invalid hda_soc_ssdt_quirks
Drop the hda_soc_ssdt_quirks function since it doesn't apply for any of the SoCs supported by the Stoneyridge code which was the only SoC implementing it. This code was added when commit 91a7abf25c72 ("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") rewrote the code originally added in commit 1587dc8a2b4d ("soc/amd/stoneyridge: Add northbridge support") as a copy from northbridge/amd/pi/00670F00. This code was moved around in commit 6580408a7e0a ("amd/pi/hudson: Move audio to northbridge"), since the HDA controller was moved from the FCH to the northbridge complex. When the controller was moved, the PCI config space interface also changed, so those bits are no longer the DisableNoSnoop, DisableNoSnoopOverride, and EnableNoSnoopRequest bits of the Misc Control register of the HDA controller, but some bits within the ClassCodeW field of the ACGAZ Mirrot Reg Ctrl 0 register. BKDG #55072 Rev 3.04 (Stoneyridge), BKDG #50742 Rev 3.08 (family 15h model 60h-6fh / 00670F00), and BKDG #52740 Rev 3.05 (family 16h model 30h-3fh) were used as a reference. Only the SoC with BKDG #52740 still has the HDA controller in the FCH; the other two have it in the northbridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77fc76752b1c7de62ba8a196f15c198f55be3074 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78940 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/turbo')
0 files changed, 0 insertions, 0 deletions