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| author | Werner Zeh <werner.zeh@siemens.com> | 2019-02-01 12:39:40 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-02-05 06:34:53 +0000 |
| commit | d7e5f4b7c50eacf033154e2514a6bef3db80d4b5 (patch) | |
| tree | 04079ece4b71f492395d606c35e2a018574eed0f /src/cpu/intel/speedstep | |
| parent | 279afdc24b3c65275cad222be53b908bb0f752ef (diff) | |
mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5
These boards need a working VTD therefore enable this feature.
Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/cpu/intel/speedstep')
0 files changed, 0 insertions, 0 deletions