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authorStefan Reinauer <reinauer@chromium.org>2012-07-23 16:12:52 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-25 22:23:40 +0200
commit6d29c7352f4d410f75e740f3dd13de813107f1bd (patch)
tree76508a5af13e78e020b70e7317cc46646f718c75 /src/cpu/intel/speedstep
parentdcc17ae3702b942ef67ebe194d6e9e560de127ef (diff)
Include SandyBridge Microcode when IvyBridge is enabled
.. in case the system has pluggable CPUs or might come in different SKUs. Change-Id: I7a7cd95b4de5dd78370355f448688e8d000434c1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1333 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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