diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-11-23 21:23:44 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-11-30 17:21:17 +0000 |
| commit | 242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab (patch) | |
| tree | bd104e859220d84d30f56c3acb689ff7e0ca17b9 /src/cpu/intel/speedstep | |
| parent | 3df9dbe8864adf6d41df2fe617c8818d1bad9d42 (diff) | |
intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/speedstep')
| -rw-r--r-- | src/cpu/intel/speedstep/speedstep.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 96ac8e59e0..441f2a36af 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -55,15 +55,15 @@ static void speedstep_get_limits(sst_params_t *const params) /* Read normal maximum parameters. */ /* Newer CPUs provide the normal maximum settings in - IA32_PLATFORM_ID. The values in IA32_PERF_STS change + IA32_PLATFORM_ID. The values in IA32_PERF_STATUS change when using turbo mode. */ msr = rdmsr(IA32_PLATFORM_ID); params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); if (cpu_id == 0x006e) { /* Looks like Yonah CPUs don't have the frequency ratio in - IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading + IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading should be reliable as those CPUs don't have turbo mode. */ - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK) >> SPEEDSTEP_RATIO_SHIFT; } |