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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-02-16 23:12:04 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-03-31 11:58:51 +0200 |
| commit | 05d6ffba0f33926eb74e104a1ab86e474b5dd71b (patch) | |
| tree | 5f85b227e44024146d3f6561c78ddc112727b1f5 /src/cpu/intel/speedstep | |
| parent | 7dfe32c5408916b6cb23f1ec48e473e1c728d300 (diff) | |
Intel cpus: improve CPU compatibility of new CAR
Most or many Xeons have no MSR 0x11e.
I have previously tested that a HT-enabled P4 (model f25) can
execute this but will not have cache-as-ram enabled. Should work
for non-HT P4.
Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/644
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/speedstep')
0 files changed, 0 insertions, 0 deletions