diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-06 18:40:23 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-17 17:09:13 +0000 |
| commit | 0a4e0fd913006de8f5d0a4ea24e013f30243cf5c (patch) | |
| tree | 47d8e59bd239a7b6b74d25393f9e3efe6cf1e223 /src/cpu/intel/speedstep/acpi | |
| parent | 30bba281b9b4330f5fadf36d187c2512f94c29e0 (diff) | |
cpu/intel/speedstep: Fix the PNOT ACPI method
The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/speedstep/acpi')
| -rw-r--r-- | src/cpu/intel/speedstep/acpi/cpu.asl | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl new file mode 100644 index 0000000000..9ff3f76727 --- /dev/null +++ b/src/cpu/intel/speedstep/acpi/cpu.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) +External (\_PR_.CP00, DeviceObj) +External (\_PR_.CP00._PPC) +External (\_PR_.CP01._PPC) + +Method (PNOT) +{ + If (MPEN) { + \_PR.CNOT (0x80) // _PPC + Sleep(100) + \_PR.CNOT (0x81) // _CST + } Else { // UP + Notify (\_PR_.CP00, 0x80) + Sleep(0x64) + Notify(\_PR_.CP00, 0x81) + } +} |