diff options
| author | Boris Mittelberg <bmbm@google.com> | 2021-03-25 22:34:28 +0000 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-04-02 16:10:27 +0000 |
| commit | 6c2f80c4a2ea39679c80368387d8a20854a985b2 (patch) | |
| tree | 2848a7998267f40944d9944dfa6b4ce40ded0ecd /src/cpu/intel/speedstep/acpi.c | |
| parent | 65fce098e3d4ba7b884bee040885acf8b44d05c2 (diff) | |
mainboard/google/brya: Enable tight timestamp
This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for
CREC device
BUG=none
TEST=manual test
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/cpu/intel/speedstep/acpi.c')
0 files changed, 0 insertions, 0 deletions