diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-27 00:34:18 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-08 23:39:22 +0100 |
| commit | 306521b82ef522c1df876b229d462359e920d8ef (patch) | |
| tree | df29b3e5ea020a365fd5868a42784344a43205fe /src/cpu/intel/socket_mPGA478MN | |
| parent | be913983534a340cce81ad9da084abec9ff6311b (diff) | |
cpu/intel/socket_mPGA478MN: Add socket P
This mobile CPU socket supports model_6fx and model_1067x.
Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17154
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel/socket_mPGA478MN')
| -rw-r--r-- | src/cpu/intel/socket_mPGA478MN/Kconfig | 18 | ||||
| -rw-r--r-- | src/cpu/intel/socket_mPGA478MN/Makefile.inc | 14 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig new file mode 100644 index 0000000000..7c4dbc5b29 --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Kconfig @@ -0,0 +1,18 @@ +config CPU_INTEL_SOCKET_MPGA478MN + bool + select CPU_INTEL_MODEL_1067X + select CPU_INTEL_MODEL_6FX + select MMX + select SSE + +if CPU_INTEL_SOCKET_MPGA478MN + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc new file mode 100644 index 0000000000..407861e164 --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc @@ -0,0 +1,14 @@ +subdirs-y += ../model_6fx +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +romstage-y += ../car/romstage.c |