summaryrefslogtreecommitdiff
path: root/src/cpu/intel/socket_mFCPGA478
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 10:00:28 +0300
committerMartin Roth <martinroth@google.com>2016-06-21 00:49:12 +0200
commit15fa992cc8467b4cbd8ebea62e3e4c947827137e (patch)
tree99e598cc9f4d088a57e04218f2f979a83a6158d6 /src/cpu/intel/socket_mFCPGA478
parent4c3de9c3edd7cb6fabc72337171862930354f0bf (diff)
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/socket_mFCPGA478')
-rw-r--r--src/cpu/intel/socket_mFCPGA478/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index 749f6abf06..6056d3c453 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -12,3 +12,4 @@ subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c