diff options
| author | Nico Huber <nico.huber@secunet.com> | 2019-02-27 14:23:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-28 13:47:54 +0000 |
| commit | 4829af17e3171da803532e9757100cc9f70d70ec (patch) | |
| tree | 1d27d26c975a9e5670c6270e482a343d4c42d112 /src/cpu/intel/socket_m | |
| parent | 620e0f3f22059eae2c7ce0d272a3eca47a6c1de5 (diff) | |
cpu/intel: Rename socket_mFCPGA478 to socket_m
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.
The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.
Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/intel/socket_m')
| -rw-r--r-- | src/cpu/intel/socket_m/Kconfig | 23 | ||||
| -rw-r--r-- | src/cpu/intel/socket_m/Makefile.inc | 17 |
2 files changed, 40 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig new file mode 100644 index 0000000000..aadc9a47b0 --- /dev/null +++ b/src/cpu/intel/socket_m/Kconfig @@ -0,0 +1,23 @@ +config CPU_INTEL_SOCKET_M + bool + +if CPU_INTEL_SOCKET_M + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_INTEL_MODEL_69X + select CPU_INTEL_MODEL_6DX + select CPU_INTEL_MODEL_6EX + select CPU_INTEL_MODEL_6FX + select MMX + select SSE + +config DCACHE_RAM_BASE + hex + default 0xfefc0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc new file mode 100644 index 0000000000..139b1bb624 --- /dev/null +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -0,0 +1,17 @@ +subdirs-y += ../model_69x +subdirs-y += ../model_6dx +subdirs-y += ../model_6ex +subdirs-y += ../model_6fx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep + +cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S +postcar-y += ../car/p4-netburst/exit_car.S + +romstage-y += ../car/romstage.c |