diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 23:34:13 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:45:48 +0000 |
commit | e27c013f39f0433dac57a754b3484553a536f30d (patch) | |
tree | 6e9b9d20964ac994c453079ca9c13cb145480dbd /src/cpu/intel/socket_m | |
parent | dc584c3f221bb59ee6b89e5517617b9d1d74bcf3 (diff) |
nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK
Console init in bootblock will be done in a separate CL.
Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/socket_m')
-rw-r--r-- | src/cpu/intel/socket_m/Kconfig | 8 | ||||
-rw-r--r-- | src/cpu/intel/socket_m/Makefile.inc | 3 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 02330f9cb8..8b1f5edda5 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -18,4 +18,12 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + endif diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 96f16dc6b3..61e4e58f13 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -9,7 +9,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S +bootblock-y += ../car/core2/cache_as_ram.S +bootblock-y += ../car/bootblock.c postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c |