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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-17 17:22:51 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-02 21:57:51 +0000 |
| commit | 6a8ce0d250f4dbaa2f253e566cf76e20f753d131 (patch) | |
| tree | 47e81bd475098c3b8e411eafc677bc76951bd2db /src/cpu/intel/socket_LGA775 | |
| parent | 8168046432b5bd3da213f7b00beb80543123bab3 (diff) | |
cpu/intel/car: Prepare for some POSTCAR_STAGE support
The file cache_as_ram_ht.inc is used across a variety
of CPUs and northbridges. We need to split it anyway
for future C_ENVIRONMENT_BOOTBLOCK and verstage work.
Split and rename the files, remove code that is globally
implemented in POSTCAR_STAGE framework already.
Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/socket_LGA775')
| -rw-r--r-- | src/cpu/intel/socket_LGA775/Makefile.inc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ffcd1cb33e..7ff2f33f3f 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,6 +13,10 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep +ifneq ($(CONFIG_POSTCAR_STAGE),y) cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -romstage-y += ../car/romstage.c +else +cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +postcar-y += ../car/p4-netburst/exit_car.S +endif romstage-y += ../car/romstage.c |