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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:00:28 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:49:12 +0200 |
| commit | 15fa992cc8467b4cbd8ebea62e3e4c947827137e (patch) | |
| tree | 99e598cc9f4d088a57e04218f2f979a83a6158d6 /src/cpu/intel/socket_LGA775 | |
| parent | 4c3de9c3edd7cb6fabc72337171862930354f0bf (diff) | |
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/socket_LGA775')
| -rw-r--r-- | src/cpu/intel/socket_LGA775/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 54a762eb44..371a801425 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -16,3 +16,4 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc romstage-y += ../car/romstage.c +romstage-y += ../car/romstage.c |