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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-11 23:56:51 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-15 11:38:01 +0000 |
| commit | 19e7273ec2dc243b4089b9aeeaf7929ff5a20a34 (patch) | |
| tree | 98894887d49e25e325f9d87eb9677e932d112400 /src/cpu/intel/socket_FCBGA559/Kconfig | |
| parent | 0feaa85233c099b06f84d5a0e1d82575efdba56b (diff) | |
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.
This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/socket_FCBGA559/Kconfig')
| -rw-r--r-- | src/cpu/intel/socket_FCBGA559/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index d1cc80f7bc..6566a01cf8 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -1,5 +1,7 @@ config CPU_INTEL_SOCKET_FCBGA559 bool + help + Select this socket on Intel Pineview if CPU_INTEL_SOCKET_FCBGA559 @@ -8,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_INTEL_MODEL_106CX select MMX select SSE + select CPU_HAS_L2_ENABLE_MSR config DCACHE_RAM_BASE hex |