cpu/intel/model_206ax: Use parallel MP init

This patch adds a few southbridge calls needed for parallel MP init.

Moves the smm_relocate() function to smm/gen1/smi.h, since that is
where this function is defined now.

Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU.

Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25618
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 94 insertions, 0 deletions

diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index cc6811fd63..6d08bb3684 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -11,6 +11,10 @@
  * GNU General Public License for more details.
  */
 
+#include <device/device.h>
+
+void bsp_init_and_start_aps(struct bus *cpu_bus);
+
 /* These helpers are for performing SMM relocation. */
 void southbridge_smm_init(void);
 void southbridge_trigger_smi(void);
@@ -21,3 +25,12 @@ int cpu_get_apic_id_map(int *apic_id_map);
 void northbridge_write_smram(u8 smram);
 
 bool cpu_has_alternative_smrr(void);
+
+/* parallel MP helper functions */
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		size_t *smm_save_state_size);
+void smm_initialize(void);
+void southbridge_smm_clear_state(void);
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+			uintptr_t staggered_smbase);
+void smm_relocate(void);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 105b9a45ca..4b824a57a5 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -22,10 +22,12 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <console/console.h>
+#include <smp/node.h>
 #include "smi.h"
 
 #define SMRR_SUPPORTED (1 << 11)
@@ -349,3 +351,82 @@ void smm_lock(void)
 
 	northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG);
 }
+
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		size_t *smm_save_state_size)
+{
+	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+	fill_in_relocation_params(&smm_reloc_params);
+
+	if (CONFIG_IED_REGION_SIZE != 0)
+		setup_ied_area(&smm_reloc_params);
+
+	*perm_smbase = smm_reloc_params.smram_base;
+	*perm_smsize = smm_reloc_params.smram_size;
+	*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
+}
+
+void smm_initialize(void)
+{
+	/* Clear the SMM state in the southbridge. */
+	southbridge_smm_clear_state();
+
+	/*
+	 * Run the relocation handler for on the BSP to check and set up
+	 * parallel SMM relocation.
+	 */
+	smm_initiate_relocation();
+}
+
+/* The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here. */
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+				uintptr_t staggered_smbase)
+{
+	msr_t mtrr_cap;
+	struct smm_relocation_params *relo_params = &smm_reloc_params;
+	em64t101_smm_state_save_area_t *save_state;
+	u32 smbase = staggered_smbase;
+	u32 iedbase = relo_params->ied_base;
+
+	printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+
+	/* Make appropriate changes to the save state map. */
+	if (CONFIG_IED_REGION_SIZE != 0)
+		printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
+		       smbase, iedbase);
+	else
+		printk(BIOS_DEBUG, "New SMBASE=0x%08x\n",
+		       smbase);
+
+	save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
+			sizeof(*save_state));
+	save_state->smbase = smbase;
+	save_state->iedbase = iedbase;
+
+	/* Write EMRR and SMRR MSRs based on indicated support. */
+	mtrr_cap = rdmsr(MTRR_CAP_MSR);
+	if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0)
+		write_smrr(relo_params);
+}
+
+/*
+ * The default SMM entry can happen in parallel or serially. If the
+ * default SMM entry is done in parallel the BSP has already setup
+ * the saving state to each CPU's MSRs. At least one save state size
+ * is required for the initial SMM entry for the BSP to determine if
+ * parallel SMM relocation is even feasible.
+ */
+void smm_relocate(void)
+{
+	/*
+	 * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
+	 * shall take place. Run the relocation handler a second time on the
+	 * BSP to do the final move. For APs, a relocation handler always
+	 * needs to be run.
+	 */
+	if (!boot_cpu())
+		smm_initiate_relocation();
+}