diff options
| author | Marc Jones <marcj303@gmail.com> | 2017-08-06 17:42:35 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-14 19:36:50 +0000 |
| commit | 6bfcf666b08fcfd3f163674fcc37f4bbd9b62a30 (patch) | |
| tree | d7ff0ae3a1dd42c0e1835bc9dc13021b2f39bfb6 /src/cpu/intel/smm | |
| parent | 029dfff30cc468b3e21c2004a135d3380a8c20e6 (diff) | |
stoneyridge: Fix CPU ASL \_PR table
The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region
and length.
Fix on Kahlee, where the EC overlaps the region:
[ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16
BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.
Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/smm')
0 files changed, 0 insertions, 0 deletions