diff options
| author | Nico Huber <nico.huber@secunet.com> | 2016-10-08 18:42:46 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-10-11 11:37:10 +0200 |
| commit | 6f8b7df8ab69cd2be7d024dfbd7fbeb3a684c6b3 (patch) | |
| tree | 3060c73ee0303ecb638fc9d80ce5268010855504 /src/cpu/intel/smm/gen1/smi.h | |
| parent | c9848a82e23f826adb97a251031b0625e9809b24 (diff) | |
cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE
An epic battle to fix Nehalem finally ended when we found an odd mask
set in SMRR. This was caused by a wrong calculation of TSEG size. It
was assumed that TSEG spans the whole space between TSEG base
and GTT. This is wrong as TSEG base might have been aligned down.
TEST: On X201, copied 1GiB from usb key to sd-card and verified.
Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7
Found-by: Alexander Couzens, Nico Huber
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16939
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/smm/gen1/smi.h')
| -rw-r--r-- | src/cpu/intel/smm/gen1/smi.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 49009ab0d1..c328eae91a 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -15,6 +15,6 @@ void southbridge_smm_init(void); void southbridge_trigger_smi(void); void southbridge_clear_smi_status(void); -void northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size); +u32 northbridge_get_tseg_base(void); int cpu_get_apic_id_map(int *apic_id_map); void northbridge_write_smram(u8 smram); |