diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2013-07-08 16:23:54 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 22:36:59 +0200 |
| commit | 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c (patch) | |
| tree | 6bd8440a05f6ea1184c0a5500d43cc92ab683f01 /src/cpu/intel/slot_1 | |
| parent | 0cb07e3476d9408d0935253f9f26c0a8ddc28401 (diff) | |
cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/slot_1')
| -rw-r--r-- | src/cpu/intel/slot_1/l2_cache.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index eca0c89e3b..a974d24c3d 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -34,7 +34,7 @@ */ /* This code is ported from coreboot v1. - * The L2 cache initalization sequence here only apply to SECC/SECC2 P6 family + * The L2 cache initialization sequence here only apply to SECC/SECC2 P6 family * CPUs with Klamath (63x), Deschutes (65x) and Katmai (67x) cores. * It is not required for Coppermine (68x) and Tualatin (6bx) cores. * It is currently not known if Celerons with Mendocino (66x) core require the @@ -295,7 +295,7 @@ int write_l2(u32 address, u32 data) // data1 = ffffffff // data2 = 000000dc // address = 00aaaaaa - // Final address signalled: + // Final address signaled: // 000fffff fff000c0 000dcaaa aaa00000 data1 = data & 0xff; data1 = data1 << 21; @@ -343,7 +343,7 @@ int test_l2_address_alias(u32 address1, u32 address2, /* Calculates the L2 cache size. * - * Reference: Intel(R) 64 and IA-32 Architectures Software Developer’s Manual + * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. * */ |