diff options
| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-06 23:14:54 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-01-16 05:34:25 +0100 |
| commit | 2c38f50b4ad8850676a70427bf1e2e9e9aab82a4 (patch) | |
| tree | 68fe15f5e270e69ab9810b12fa2bf61d7ff71585 /src/cpu/intel/model_f3x | |
| parent | b4c39902edbba61827c60a75fe84e748e217b8be (diff) | |
cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.
The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.
The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.
Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_f3x')
| -rw-r--r-- | src/cpu/intel/model_f3x/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_f3x/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_f3x/microcode_blob.c | 16 | ||||
| -rw-r--r-- | src/cpu/intel/model_f3x/model_f3x_init.c | 19 |
4 files changed, 20 insertions, 18 deletions
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 4cfca83dc6..8ae2dcff29 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F3X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index cf8f918514..ebd47cfcf8 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f3x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c new file mode 100644 index 0000000000..0bd2a5b4b0 --- /dev/null +++ b/src/cpu/intel/model_f3x/microcode_blob.c @@ -0,0 +1,16 @@ +unsigned microcode_updates_f3x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + +#include "microcode-1290-m0df320a.h" +#include "microcode-1467-m0df330c.h" +#include "microcode-1468-m1df3417.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 2504ba9423..5752347943 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -10,23 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - -#include "microcode-1290-m0df320a.h" -#include "microcode-1467-m0df330c.h" -#include "microcode-1468-m1df3417.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f3x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -38,7 +21,7 @@ static void model_f3x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ |