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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-09-26 10:26:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-01 15:10:16 +0000 |
| commit | 6e079dc120a4aa95a25cfe536d4b1acd178918fd (patch) | |
| tree | c8b1d76e5dd361964389c0f628b162102e72add1 /src/cpu/intel/model_f3x | |
| parent | 5adbc767f66224e617b6c8204a868542b8010999 (diff) | |
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread
on HyperThreading enabled platforms, to prevent race conditions and
resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_f3x')
| -rw-r--r-- | src/cpu/intel/model_f3x/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_f3x/model_f3x_init.c | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 7eaa820772..9a5e2a1caf 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,5 @@ config CPU_INTEL_MODEL_F3X select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index d348df6c82..48e3872225 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -17,6 +17,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/cache.h> static void model_f3x_init(struct device *cpu) |