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| author | Robert Zieba <robertzieba@google.com> | 2022-08-10 16:31:27 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-09 23:57:49 +0000 |
| commit | 44281956928348bb5df14a8257921c49991dace5 (patch) | |
| tree | 0b213a12e21276a70159f0614b38f36987903d22 /src/cpu/intel/model_f2x | |
| parent | 065c5870e4678367f5be7014361772c9d03933c8 (diff) | |
device/xhci: Factor out common PORTSC code
This commit factors out some code for XHCI port status values.
BUG=b:186792595
TEST=Built coreboot for volteer device
Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_f2x')
0 files changed, 0 insertions, 0 deletions