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| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-05-19 09:55:20 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-20 11:21:11 +0000 |
| commit | e1c385ebe142845012e0a844d798fa7268c1cfd8 (patch) | |
| tree | 4ed8400c0ea1036f8cb218007c732456becb49aa /src/cpu/intel/model_6xx | |
| parent | 100514d8c7fdfea17de938cddc63f1457dd3af3a (diff) | |
mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface type
Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix
logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN
SGMII as the original intention is to set the PSE TSN phy
interface as RGMII.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/cpu/intel/model_6xx')
0 files changed, 0 insertions, 0 deletions