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authorKeith Hui <buurin@gmail.com>2019-12-09 20:25:16 -0500
committerNico Huber <nico.h@gmx.de>2020-01-18 22:07:47 +0000
commita988091d395ac59639329161a0d500995886e192 (patch)
tree6bd37b8ccfd2da315ebfb306592d0df8cf995f70 /src/cpu/intel/model_6xx
parent39e1f44f331040b2e9574e9c792f583b8c6a5aba (diff)
cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
These predate hyperthreading so they are not SMP capable unless installed in a SMP board. Turning SMP off shaves 128 compressed bytes from ramstage. Change-Id: I114bdc83ed40ccd9d3996aabf77422236d9d12fa Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_6xx')
-rw-r--r--src/cpu/intel/model_6xx/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig
index 7cafb81e60..d00fc2436a 100644
--- a/src/cpu/intel/model_6xx/Kconfig
+++ b/src/cpu/intel/model_6xx/Kconfig
@@ -4,5 +4,4 @@ config CPU_INTEL_MODEL_6XX
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
- select SMP
select SUPPORT_CPU_UCODE_IN_CBFS