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authorArthur Heymans <arthur@aheymans.xyz>2018-07-21 15:03:06 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-01-24 13:42:36 +0000
commitdf7aecd92643d207feaf7fd840f8835097346644 (patch)
tree86ca82a7935bf26bd3edd8971f60df63948fad95 /src/cpu/intel/model_6fx
parent845a96dfd601c08f2d5c2cf362a7021f912c4857 (diff)
cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR
Some CPUs, (Intel core2 and pineview) have slightly different SMRR MTRR mechanism. The MSR_SMRR_PHYSBASE/MASK MSRs are at a different location, have slightly different semantics and need SMRR enable in a locked down IA32_FEATURE_CONTROL MSR. This change takes away the possibility to (not) lock IA32_FEATURE_CONTROL on these CPUs, as this is needed for SMRR MSR to work. Since sockets cover multiple CPUs of which only some support SMRR, the Kconfig option CONFIG_SET_IA32_FC_LOCK_BIT is kept in place, even though it gets meaningless on those CPUs. Locking that bit was the default anyway. With this patch Intel Netburst CPUs also configure IA32_FEATURE_CONTROL. According to Intel 64 and IA-32 Architectures Software Developer's Manual those CPUs support that MSR so issues are not to be expected. Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27586 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/model_6fx')
-rw-r--r--src/cpu/intel/model_6fx/model_6fx_init.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 16ddcc4c28..4e198961ce 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -139,9 +139,6 @@ static void model_6fx_init(struct device *cpu)
/* Enable the local CPU APICs */
setup_lapic();
- /* Set virtualization based on Kconfig option */
- set_vmx_and_lock();
-
/* Configure C States */
configure_c_states();